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[Bob Schwenkler]

i started reading the "proper word clock implementation" thread, and a thought came up that i have been wondering about for a while.

if i am synching a device to optical adat, does the device perform a similar operation as with wc? does it run through a pll and reclock itself internally (i still am not totally clear though on what exactly plls do).

simply put: what happens when i slave a device's clock to an optical feed?

[Nika Aldrich]

Yes,

Still goes through a PLL and reclocks it internally.

Think of a PLL like a device that looks at the external clock and the internal clock and figures out how in sync they are and then sends electrical messages to the internal clock telling it to speed up or slow down commensurately.  So if the external clock is faster than the internal clock the PLL tells the internal clock to slow down until they are in sync, etc.

At issue is the "speed" of the PLL, or its reaction time.  If the PLL is very slow to get the internal clock to adjust then some of the rampant behavior of the external clock can effectively be eliminated just because of the buffering of this slow moving PLL>  On the other hand, if the PLL is TOO slow then the two clocks can fall out of sync. T he trick is to have the PLL generally be as slow as manageable but not so slow as to fall out of sync.  If the PLL is very fast - say has an instantaneously fast reaction time getting the internal clock to adjust - then any erratic behavior from the external clock will get manifested identically in the internal clock, negating the need for the PLL at all - might as well just sync to the external clock at that point.

Does this make sense?

Nika

[Eric Martinez]

How good (or bad) is clocking through optical (spdif) compared to WC or AES?

[Bob Schwenkler]

that makes sense. thats pretty much what i thought it was... could you explain why a pll has intrinsically worse performance than an internal master clock?

i was also thinking that to minimize jitter in a pll, you could put another pll after the first one. sort of like a second stage of jitter filtration... is this done?

that thread i was reading seems to have dissappeared. oh well...

[Nika Aldrich]

chikkenguy wrote on Fri, 01 April 2005 12:39

that makes sense. thats pretty much what i thought it was... could you explain why a pll has intrinsically worse performance than an internal master clock?

The A/D chip does not actually use a 44.1kHz master clock.  It uses something like a 2.8MHz master clock, so the actual clock signal needs to be at this rate.  This is much too high, however, for transmitting through 10' cables with any accuracy.  So instead, the clock is generated at this rate in an external box, converted down to 44.1kHz, transmitted through a 10' cable, then the PLL not only slaves an internal clock to it, but also upsamples it as well back to 2.8MHz as well.

The question is, which is better?:

A. internal chip running at 2.8MHz sends a clock pulse about 1" on a circuit board trace, or
B. external box has a clock running at 2.8MHz, converts it to 44.1KHz, sends it through a 10' cable to another device (through connectors and whatnot, in the middle of a noise EMI/RFI environment), which uses a PLL to try to both reduce jitter artifacts but also to raise it back to 2.8MHz, and then sends it 1" on a circuit board trace.

Quote:

i was also thinking that to minimize jitter in a pll, you could put another pll after the first one. sort of like a second stage of jitter filtration... is this done?

If the first PLL is designed to allow the slowest response that is possible, then putting a second one after that effectively doubles the response time and makes it too long - the clocks can fall out of sync.  Better to have one PLL that is tuned to provide the maximum amount of buffering short of falling out of sync.

Nika

[Bob Schwenkler]

Nika Aldrich wrote on Fri, 01 April 2005 10:09

The A/D chip does not actually use a 44.1kHz master clock.  It uses something like a 2.8MHz master clock, so the actual clock signal needs to be at this rate.  This is much too high, however, for transmitting through 10' cables with any accuracy.

what are the issues with high frequencies through cables? i looked briefly at the "skin effect" thread. i have not heard of this phenomenon before today. are these two things related? or is it other simpler things like resistance/inductance that hamper high frequency transmission in longer (like 10') cables?

[Bob Schwenkler]

Nika Aldrich wrote on Fri, 01 April 2005 10:09

The A/D chip does not actually use a 44.1kHz master clock.  It uses something like a 2.8MHz master clock, so the actual clock signal needs to be at this rate.  This is much too high, however, for transmitting through 10' cables with any accuracy.

also, im not sure exactly what you mean by "accuracy" here. do you mean accuracy of timing?

[Nika Aldrich]

chikkenguy wrote on Fri, 01 April 2005 13:38

what are the issues with high frequencies through cables? i looked briefly at the "skin effect" thread. i have not heard of this phenomenon before today. are these two things related? or is it other simpler things like resistance/inductance that hamper high frequency transmission in longer (like 10') cables?

Yeah, it's the other stuff - the inherent low pass filtering of a cable combined with HF noise imparted in the clock signal.  Clock pulses are supposed to be square waves.  Square waves are the summation of the odd harmonics of a fundamental.  Think of the frequencies involved for a 44.1kHz signal as opposed to a 2.8224MHz signal.  The less the waveform is square the more susceptible it is to jitter, so by keeping the frequency of the clock lower we reduce the susceptibility to jitter in that cable.

Nika

[Nika Aldrich]

chikkenguy wrote on Fri, 01 April 2005 13:44

also, im not sure exactly what you mean by "accuracy" here. do you mean accuracy of timing?

Yes.  Accuracy of the timing.  

[danlavry]

Nika Aldrich wrote on Fri, 01 April 2005 19:52

chikkenguy wrote on Fri, 01 April 2005 13:38 what are the issues with high frequencies through cables? i looked briefly at the "skin effect" thread. i have not heard of this phenomenon before today. are these two things related? or is it other simpler things like resistance/inductance that hamper high frequency transmission in longer (like 10') cables? Yeah, it's the other stuff - the inherent low pass filtering of a cable combined with HF noise imparted in the clock signal.  Clock pulses are supposed to be square waves.  Square waves are the summation of the odd harmonics of a fundamental.  Think of the frequencies involved for a 44.1kHz signal as opposed to a 2.8224MHz signal.  The less the waveform is square the more susceptible it is to jitter, so by keeping the frequency of the clock lower we reduce the susceptibility to jitter in that cable. Nika

Yes, a square wave is made of odd harmonics but how does that statment apply to jitter and rise time? You conclusion is incorrect. Keeping the clock frequency low does not reduce susceptibility to jitter due to harmonics content. The rise time of a 1KHz signal and 1MHz signal is the same if they are both limited by say 100MHz bandwidth.

True, the 1MHz square wave has only 50 odd harmonics to 100MHz and the 1KHz signal has 50000 harmonics, but the rise time is determined by the upper bandwidth limit, not by the number of harmonics.

Of course there are other issues besides "how many harmonics"
that matter. I am only replying to your "harmonic content" stament.

Regards
Dan Lavry
www.lavryengineering.com