Print

Please login or register.
1 Hour 1 Day 1 Week 1 Month Forever
Login with username, password and session length

[Jon Halverson]

What would be the reason to provide wordclock input on a device that only has analog and AES3 inputs (e.g. power amplifier).  Provided that the designer of the device knew how to design a decent AES3 clock recovery circuit.

Any thoughts, or scenarios that I may not have considered?

jon

[bruno putzeys]

Jon Halverson wrote on Thu, 24 April 2008 22:36

Provided that the designer of the device knew how to design a decent AES3 clock recovery circuit.

What do you consider a "decent AES3 clock recovery circuit" and how many devices contain such a thing? Most devices known to be quite insensitive to AES3 jitter actually have an SRC inside, so that does not bode well for the majority of clock recovery circuits.

[Jon Halverson]

Bruno Putzeys wrote on Fri, 25 April 2008 01:24

What do you consider a "decent AES3 clock recovery circuit" and how many devices contain such a thing? Most devices known to be quite insensitive to AES3 jitter actually have an SRC inside, so that does not bode well for the majority of clock recovery circuits.

Im thinking of a VCXO based PLL with a nice low corner, and maybe a "fast lock" feature so the user doesn't have to wait too long. The DAC would be something like CS4398

Are you suggesting that you would rather have an SRC?

My question is more of a "marketing" one.  Does the user want, or need, wordclock inputs in an output device.  Is the only reason because there is so much gear with poor clock recovery performance otherwise? Neither Yamaha nor Lab Gruppen provide wordclock on their amps that have AES3 inputs.

(random thought)
It cant be cheaper to add the separate wordclock input since there is still a PLL needed to generate MCLK. Unless the design used a single VCO to cover base 44.1k, an 48k sample rates maybe.

jon

[bruno putzeys]

VCXO's aren't a common occurrence in normally priced gear.

If you're planning a DAC, a digital-input power amp or an active speaker (i.e. something with no digital outputs) I wouldn't bother with a word sync input. Not if you're at liberty of designing a good PLL. The point of having a word sync input is to synchronise devices together that have digital outputs and to prevent accumulation of jitter.
Although a surprising amount of kit has improved clock stability when locked to an external word sync (while some others deteriorate), I don't think putting a word sync on a newly designed box "for sound quality reasons" alone is a good idea.

An ASRC as a dejittering device is only a good idea in "end station" devices like DACs etc. It is therefore not a universal alternative to a good PLL.

[Jon Halverson]

Bruno Putzeys wrote on Fri, 25 April 2008 08:40

VCXO's aren't a common occurrence in normally priced gear.

wow, really?  I'm relatively new to digital audio design, and mostly self taught on these issues.  I guess it always surprises me the kinds of half-assed designs people get away with.  [sigh]

A VCXO is not that expensive.  Are people just using the RMCLK straight off the AES Rx chip?

thanks Bruno!

Are you coming over to speak at AES in the fall?

jon

[bruno putzeys]

Jon Halverson wrote on Fri, 25 April 2008 19:49

Are people just using the RMCLK straight off the AES Rx chip?

Some are. Some have discrete (non-crystal-based) PLL's. Some have an SRC that's always on. The good news is that there are now chips like the Dice series that have a very high-quality digitally synthesised PLL.

Jon Halverson wrote on Fri, 25 April 2008 19:49

Are you coming over to speak at AES in the fall?

No speaking engagement yet. At the very least I'll be there in my usual function as Hypex&Grimm booth gnome.

[Larrchild]

I just realized that I have a DDS (Direct Digital Synthesis) 1-50 MHz oscillator that uses the AD9850 DDS chip. Would that make a better (lower phase noise) signal than a good crystal oscillator?
Not sure what it's clocking at but it's probably a high frequency.

Seems not too bad here, this is the AD9834, not the AD9850:


Typical output phase noise plot for the AD9834. Output frequency is 2 MHz and M clock is 50 MHz.

  http://www.analog.com/library/analogDialogue/archives/38-08/ dds.html

[bruno putzeys]

It won't get stabler than the crystal oscillator you're using to drive it. What you can do with DDS is take a very stable (but un-pullable) master oscillator and use it to generate equally stable clocks at arbitrary frequencies. That in turn can be rolled into a digitally controlled PLL if needed. One should be on one's guard for nonrandom spuriae though, especially if the ratio between the master clock and the synthesised clock is nearly, but not exactly, simple. The plot you posted was for an exact 25:1 ratio, which is sure going to look good, but try a 25.01:1 ratio next. The noise floor would still be that of the master oscillator but there'll be all sorts of spikes sticking out. The linearity of the DAC used in the DDS is key, as is the lowpass filter.

DDS is used in the Audio Precision test sets (where it appears to function flawlessly), in the Mutec iClock, and in the Dice II (TC electronics) JET PLL, to name three.

[Larrchild]

Cool. That site had a interactive design tool to predict spuriae too:
http://www.analog.com/Analog_Root/static/techSupport/designT ools/interactiveTools/ad98334/ad9834.html

Looks like Big Ben uses it too:
"That's where Big Ben's new C777 clock comes in. Big Ben utilizes an entirely digital process that Apogee has developed, using the most advanced Direct Digital Synthesis (DDS) technology available along with DSP based digital filtering. The result? Big Ben has the most aggressive jitter reduction ever."
http://www.apogeedigital.com/products/bigben.php

[Bogic Petrovic]

Hi,

Is it there any precise specification, recommendation or whatever.. for input and output Word Clock digital interfaces? I think about input/output impedance...  Word Clock use BNC connector, 75ohms cable... etc... so, there is a space for some precise specification for clock drivers and receivers...

I read AES specification long ago, for digital (AES3, DARS) synchronisation, and find only that Word Clock is noted in last chapter, without precise specs... if I can remember now...


This is probably stupid question, sorry!

[bruno putzeys]

None so far. It's a disaster. Some outputs are 75ohm terminated, some are low impedance. Some inputs are 75ohm terminated, some are open or switchable. Some use TTL input levels, other CMOS, etc. There is NO standard. Dave Hill says he's in a committee to develop one, so I hope that work is progressing well.

What I do to maximise the chances of interoperating is to have a 5.5V output that's switchable between low-z (20ohms) and 75ohms, and make an input buffer that is AC coupled and that'll reliably work with 0.5V peak-peak.

[Bogic Petrovic]

Bruno Putzeys wrote on Mon, 25 August 2008 15:08

....Dave Hill says he's in a committee to develop one, so I hope that work is progressing well. ....

Well, ... good news!

IMHO, "fight" against WordClock jitter, is possibly (or slightly) premature "action", if we don't even know which interfaces (tx, rx, whatever...) we can expect to/from other devices/equipment... especially when we expected or think about excellent jitter characteristics...

AES3/DARS is based on RS-422 if I remember... I know,... this is nothing "special", but (well) defined and compatible (at least with another RS-422, or RS-485).