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Well really there is no noise component (I mentioned phase noise earlier, but that is so not the problem and so far below the noisefloor of discussion that we should drop the noise spec).
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Well, jitter has noise in that you can’t tell in advance what the time-error will be at a given instant—it is random. Is it white noise? Well, as I understand it, close-in phase noise falls off at 1/f making it more pink than white. But the fact that it is random—read not deterministic—makes it noise. And so you have to model it as a random variable. While such noise may be so low as to be uninteresting, why throw it out? If it is not interesting, then it won’t show up in the graph.
In general, the test should be as comprehensive as possible; noise should be part of the spec. Otherwise manufacturers might claim that their device is ‘better’ because it is quieter and they won’t have to defend (1) that their device is indeed quieter and (2) that it matters. In that event, we'd be back to where we started.
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It doesn't need to be modeled, really. It's a pretty straight ahead formula.
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The resulting amplitude error from a given timing error is a pretty straightforward formula, but the actual sampling time error produced by the device is not so easy. If the jitter spectrum does not have a trivial (flat) shape, then a function that produces a timing error is not trivial at all. As I mentioned, the jitter function will be some combination of perhaps many noise and periodic components.
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The two issues that we run into are the range of the jitter spectrum we are going to require in the spec, and the deviance that any downline box can have on the results. Again, much of the problem is the PLL, not the clock!
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While I haven’t thought much about the range of the jitter spectrum, I do think that the clock interfaces of downstream devices should be considered separately. Clock manufacturers have no control over what folks might be downstream of their devices.
A clock receiver should not only specify the jitter of its internal clock, but also its ability to reject incoming jitter—that’s what a PLL is supposed to do. All PLLs do to a greater or lesser extent, and that should be spec’d. I can offer no insights into how to make PLL specs more user-friendly.
-Dennis