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Author Topic: Proper word clock implementation  (Read 103502 times)

Big Bri

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Proper word clock implementation
« on: October 02, 2004, 03:08:38 am »

Dear Dan,

Man, I really appreciate you joining the forum.  Thank you so much for your time.

I've been experimenting with different word clock scenarios in our facility and am dumbfounded by the sonic differences of just changing which unit is the clock master.  One unit gives me a great clear 3d image while another is quite smeared and more 2D.

Can you please tell me why this is happening and what the best possible scenario is to set up a central word clock distribution and how to get the best results.  Also, how do you control digital units with no dedicated word clock input?(i.e. Dat machines, stand alone cd writers, outbord fx)

Once again, thanks for your time and your knowledge.
Brian
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bobkatz

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Re: Proper word clock implementation
« Reply #1 on: October 02, 2004, 04:40:42 pm »

Big Bri wrote on Sat, 02 October 2004 03:08

Dear Dan,

Man, I really appreciate you joining the forum.  Thank you so much for your time.

I've been experimenting with different word clock scenarios in our facility and am dumbfounded by the sonic differences of just changing which unit is the clock master.  One unit gives me a great clear 3d image while another is quite smeared and more 2D.

Can you please tell me why this is happening and what the best possible scenario is to set up a central word clock distribution and how to get the best results.  Also, how do you control digital units with no dedicated word clock input?(i.e. Dat machines, stand alone cd writers, outbord fx)




Dan is the man! And this is what I bet he'll tell you!

If you hear differences when you change clocks "controlling" your converters, then you have a defective converter design! A well-designed converter should contain internal phase locked loops whose performance reduces any incoming jitter artifacts to inaudibility. An external clock is a bandaid for a "cure" which can only be done properly within a good converter design. In fact, any converter which does not perform equally as good or BETTER on internal clock than external is also defective.

BK
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danlavry

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Re: Proper word clock implementation
« Reply #2 on: October 02, 2004, 05:54:02 pm »

If you hear differences when you change clocks "controlling" your converters, then you have a defective converter design! A well-designed converter should contain internal phase locked loops whose performance reduces any incoming jitter artifacts to inaudibility. An external clock is a bandaid for a "cure" which can only be done properly within a good converter design. In fact, any converter which does not perform equally as good or BETTER on internal clock than external is also defective.

BK



Yes indeed! Well said.

The best way to clock a converter is with internal clock, using a good fundamental frequency crystal (third order types are more jittery), and locating the crystal properly (good ground to the AD ample hold and so on). You now have a low jitter clock inside the machine.

What happens when you get a stand alone “almost no jitter clock”? You look AT THE OUTPUT CONNECTOR of that “super clock box” and it generally can work as well as the internal crystal clock  Now take a cable and hook it to the AD chassis. Now you have to go through some electronic circuit to receive the clock. At this point, you have accumulated a lot more jitter (I can list half a dozen causes).

Well, this is not the end of the road. The big one is the PLL circuit. Unlike the internal clock (fixed crystal case), you have a crystal that can be pulled up or down by some amount, we call it a VCXO (voltage controlled crystal oscillator). There is some circuitry in there that keeps comparing the incoming external clock rate to the VCXO, and makes the proper adjustment on an ongoing basis…
What is more steady? A mediocre internal crystal implementation is going to outdo even a good external clock implementation.

But there are times and reasons to use external clocks. For example, if one needs to sync many chassis…  

It is true that the PLL does better when fed a less jittery clock, but that is just a tiny portion of the overall issue. As Bob stated, most of the burden is on the PLL. A Good PLL, inside the AD chassis should clean most of the jitter out.

Why do you get such different results with different sources? I am not there to probe. I would not start with comparing how much jitter each source provides. I would look into issues such as driving coaxial lines, and proper termination impedance. Make sure the clock lines have no “branches” – Driver to point A, than to point B, than to C all in series.

I am no fan of distribution amplifiers either. You can not beat:
Driver to point A (with a BNC T), than to point B (with BNC T)… at the end the BNC T is terminated with the proper line impedance (if the cable is 75Ohm, so is the termination). It is a cost effective solution that yields the best results.

BR
Dan Lavry      
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bobkatz

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Re: Proper word clock implementation
« Reply #3 on: October 02, 2004, 07:25:58 pm »

danlavry wrote on Sat, 02 October 2004 17:54




Why do you get such different results with different sources? I am not there to probe.





Dan said, modestly! While adding much of Dan Lavry's designer-level substance to my short reply to the question.

I'd like to add: It is possible that you can't EVER stop getting different results with different sources unless you throw out the entire poorly-designed converter (it's mostly due to the poor PLL design within the converter, though power supply and grounding is all part of that).

Quote:



I would not start with comparing how much jitter each source provides. I would look into issues such as driving coaxial lines, and proper termination impedance. Make sure the clock lines have no ?branches? ? Driver to point A, than to point B, than to C all in series.

I am no fan of distribution amplifiers either. You can not beat:
Driver to point A (with a BNC T), than to point B (with BNC T)? at the end the BNC T is terminated with the proper line impedance (if the cable is 75Ohm, so is the termination). It is a cost effective solution that yields the best results.




I'm sure Dan would like to point out that while this is the best way to do it, each of the devices that is to receive the wordclock must have a termination on/off switch. The termination must be turned off until the end of the line, or the source will be overloaded. In other words, the last device in the line must have the 75 ohm input. Unfortunately, the VAST MAJORITY of devices and converters I've encountered do not have such a switch, or else you have to go inside and remove a jumper or in worst case desolder a termination resistor.

Dan's points are very well taken, though, and you can save a lot of costs (both hardware and performance costs) by avoiding that distribution or clock amplifier circuit and just using his BNC-T approach. But you DO have to know how to measure input impedance if in doubt whether the input word clock is truly 75 ohm.

I'd like to point out that while wordclock has potential jitter superiority over AES/EBU "black" (there's an official AES number for AES black, I forget the number) there are many problems with using wordclock when synchronizing multiple channels and/or multiple devices. There is NO STANDARD for wordclock phase! You can end up with left and right channel reversal, or even a phase shift on the output of some of your supposedly "synchronized" devices. This is why AES/EBU sync is much preferred. However, there is a much higher jitter penalty with AES/EBU sync and even more attention has to be paid to the PLL on the input of any converter which is receiving AES/EBU sync.

BK
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heinz

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Re: Proper word clock implementation
« Reply #4 on: October 03, 2004, 02:03:19 am »

bobkatz wrote on Sat, 02 October 2004 21:40

An external clock is a bandaid for a "cure" which can only be done properly within a good converter design. In fact, any converter which does not perform equally as good or BETTER on internal clock than external is also defective.


danlavry wrote on Sat, 02 October 2004 22:54

A mediocre internal crystal implementation is going to outdo even a good external clock implementation.


Wow! This thread has been very illuminating, kind of shatters some preconceptions I had. Thanks to all for the great information.
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Ozzie Bostic

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Re: Proper word clock implementation
« Reply #5 on: October 03, 2004, 10:58:44 am »

danlavry wrote on Sat, 02 October 2004 16:54

If
I am no fan of distribution amplifiers either. You can not beat:
Driver to point A (with a BNC T), than to point B (with BNC T)… at the end the BNC T is terminated with the proper line impedance (if the cable is 75Ohm, so is the termination). It is a cost effective solution that yields the best results.

BR
Dan Lavry      



Hello and Welcome Dan,

I am currently enjoy the wonderful sound and clarity of your Blue series converters great product.

My question is since your not a fan of distribution clocks; what is the maximum number of devices that should be connected in series via the BNC T method mentioned above before the clock source is degraded?

Thanks in advance.
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Albert

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Re: Proper word clock implementation
« Reply #6 on: October 03, 2004, 11:49:49 am »

Another question: Would you use a BNC t-bar and terminator on gear that is already internally terminated? Would that yield better results, or would it damage the gear?

Also, would you use a BNC t-bar on gear that has a WC in and out, or would you pass through the gear, using it's own circuitry? And if you did use the BNC t-bar to bypass the gears internal routing, would you then use a terminator on the units WC output or rely on its own termination?

Thank you, this is a great thread.
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bobkatz

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Re: Proper word clock implementation
« Reply #7 on: October 03, 2004, 01:08:13 pm »

Albert wrote on Sun, 03 October 2004 11:49

Another question: Would you use a BNC t-bar and terminator on gear that is already internally terminated? Would that yield better results, or would it damage the gear?





It wouldn't damage the gear, but eventually it would load down the source wordclock so that the system would not function or would not function well.


1) I suggest you start with an oscilloscope on the wordclock generator. Measure its output, which should be 4 v p-p if possible. Any lower and some following devices will not like it, but most following devices are comfortable with as low as 1 v p-p---
TERMINATED!!! Hey, there's no standard! It's a wild wild west.

2) Then, put a terminator on it in parallel with the scope input. The level should drop by 1/2. If not, then the source is not truly 75 ohms. This is not a big big deal with wordclock frequencies, which are not so high generally as to be subject to reflection problems. I'm sure Dan can explain the compromises there, I don't know. It would cause some limit as to the length of the cable and how many devices you can attach.

3) Using this level as your goal (2 v p-p terminated), run the signal into each of your wordclock devices and use the scope to see if the device terminates the line. Chances are it does and you'll have to go inside the device and remove the 75 ohm resistor that's there, so you can then use the BNC-T.

If the wordclock generator is truly 75 ohm, 4 v p-p (unterminated), 2 v p-p terminated, then I don't see a problem using low loss coax for even 20-40 feet and having 3 to 6 high impedance (unterminated) dropoffs in between. Scope the end of the chain. If it's still a clean square wave at approximately 2 v p-p into the terminator at the end of the chain, then I'd say it's a win-win!

Quote:



Also, would you use a BNC t-bar on gear that has a WC in and out, or would you pass through the gear, using it's own circuitry? And if you did use the BNC t-bar to bypass the gears internal routing, would you then use a terminator on the units WC output or rely on its own termination?




The problem is that most word clock equipment has internally terminated inputs and will have to be modified (real real pity, since Dan's approach is absolutely valid). If you remove the 75 ohm resistor, then you will be able to use a BNC T, as this effectively bypasses the gear's internal routing. All you are concerned with at that point is the impedance of the gear's loading. Usually it's a small coil or transformer loaded by a 75 ohm resistor. Remove the resistor and (hopefully) it becomes high impedance, that is, negligible load on the rest of the circuit.

By the way, if the equipment to be slaved is NOT a converter, but simply a digital processor or DAT machine or whatever, then a wordclock distribution amplifier will do no harm, as the interface jitter is irrelevant. I use a Lucid Clk-X to feed wordclock to my Digital Timepiece, which is NOT feeding converters, to my DAT machine, to my TC Electronic System 6000, whose converters I am not using, etc. etc.

You could take the Clk-X box, remove the input terminator, and feed using Dan's BNC-T method through the input of the Clk-X, and feed (modified unterminated) critical converters like the Digidesign, and so on, through  the BNC T system, and use the Clk-X wordclock distribution box to feed the rest of things.

My Tascam DAT machine has a Wordclock through jack and some kind of automatic termination. How does that automatic termination sensing circuit work? I don't know!!!! I don't trust it, either, but I suppose I could sniff it out with a scope...
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punkest

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Re: Proper word clock implementation
« Reply #8 on: October 03, 2004, 01:53:42 pm »

danlavry wrote on Sat, 02 October 2004 22:54




The best way to clock a converter is with internal clock,    


A mediocre internal crystal implementation is going to outdo even a good external clock implementation.



It is true that the PLL does better when fed a less jittery clock, but that is just a tiny portion of the overall issue. As Bob stated, most of the burden is on the PLL. A Good PLL, inside the AD chassis should clean most of the jitter out.

Dan Lavry      




    I thought this was only the case with older PLL that does not have reclocking circuits. I heard that many new converters used the PLL to sync and then regenerated the clock to get rid of jitter.

    Anyway, I always try to slave all to the converter?s clock, as you pointed out, Dan.

     Bob pointed out that AES sync is more jittery that WC, how would you rate the jitter when synced over ADAT optical?

     I have apogee AD. Optical cable to feed converted signals and clock to computer interfaces. Word clock cable to feed clock to Yamaha 03d console that also receive signal but no clock optically from computer interface. Would it be a better way???

     Is there potential problem with feeding parallely two sources instead of the usual serial A to B, B to C ???

Hans Mues
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bobkatz

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Re: Proper word clock implementation
« Reply #9 on: October 03, 2004, 06:20:35 pm »

[quote title=punkest wrote on Sun, 03 October 2004 13:53]
danlavry wrote on Sat, 02 October 2004 22:54





    I thought this was only the case with older PLL that does not have reclocking circuits. I heard that many new converters used the PLL to sync and then regenerated the clock to get rid of jitter.






Good PLL design really separates the men from the boys. Now Dan's not going to mention brands but I don't have an afiliation so I'll just tell you that Apogee's claims of low jitter just did not bear out. The performance did not match their claims.

All PLL's "reclock" so that's not the issue. It's "how well they do it", and how well the output performance actually works that counts. I have measurements of converters' jitter performance, both good and bad, in my book.

Quote:



     Bob pointed out that AES sync is more jittery that WC, how would you rate the jitter when synced over ADAT optical?





Doesn't ADAT really require a wordclock anyway?  If that's the case, then ADAT sync would be irrelevant, except to the extent that clocks and power and grounds can interact in a poorly-designed box.

Quote:



     I have apogee AD. Optical cable to feed converted signals and clock to computer interfaces. Word clock cable to feed clock to Yamaha 03d console that also receive signal but no clock optically from computer interface. Would it be a better way???

     Is there potential problem with feeding parallely two sources instead of the usual serial A to B, B to C ???




Hans, can you please repeat the above, more slowly  Smile.  

1) What is the block diagram of your interconnections
2) What functions as the clock master?
3) What A/D and D/A converters do you use in this block diagram and what are their functions (monitoring, mixdown, etc.)

I know that many people feel this jitter "nonsense" is overrated. But if it weren't important, why would so many people be complaining about getting "great imaging and sound with one clock and real flat sound with another". So, "the sound" must be important to a lot of people, and discovering that clocking makes a sonic difference is enough to educate people as to why and how.

That's why getting jitter right is important! However, it is important to know when jitter makes a difference and when it does not. It does not make a difference with digital to digital transfers or digital processors (EQs, compressors, etc.).

BK
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danlavry

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Re: Proper word clock implementation
« Reply #10 on: October 03, 2004, 06:27:34 pm »

Bob Katz said:
I'd like to add: It is possible that you can't EVER stop getting different results with different sources unless you throw out the entire poorly-designed converter (it's mostly due to the poor PLL design within the converter, though power supply and grounding is all part of that).


Of course. I was sort of implying that, but it is good to have it clearly stated.

I'm sure Dan would like to point out that while this is the best way to do it, each of the devices that is to receive the wordclock must have a termination on/off switch. The termination must be turned off until the end of the line, or the source will be overloaded…

Yes, thanks for reminding me of that. I decided long ago to not terminate internally, though I provide a jumper for internal termination. I guess I am not in the “vast majority” on that.  

Dan's points are very well taken, though, and you can save a lot of costs (both hardware and performance costs) by avoiding that distribution or clock amplifier circuit and just using his BNC-T approach. But you DO have to know how to measure input impedance if in doubt whether the input word clock is truly 75 ohm.

Or call the factory and ask them if the gear is internally terminated, and if so how to be sure and disconnect the internal termination. It is economically wise, or as you stated so well - save a lot of costs (both hardware and performance costs)…

I'd like to point out that while wordclock has potential jitter superiority over AES/EBU "black" (there's an official AES number for AES black, I forget the number) there are many problems with using wordclock when synchronizing multiple channels and/or multiple devices. There is NO STANDARD for wordclock phase! You can end up with left and right channel reversal, or even a phase shift on the output of some of your supposedly "synchronized" devices. This is why AES/EBU sync is much preferred.

This is the voice of experience from the field, thus very worth while points you bring up.

I am going to add some technical comments to your statements:

Is WC better than AES digital black?
Some of the “anti AES” for clock synchronization may be a “left over” from the days when people used AES with data. Such practice added a lot of jitter, but we now know we need to use a fixed pattern.
Also, as Bob stated, AES does not give you inconsistent polarity when doing a multi channel work with different gear (but is it ever a good idea?)
While AES digital black is not as bad as some people think, WC does have the advantage: The issue is signal transmission reflections (cable impedance and termination). When it comes to clocks, audio people can learn from disciplines such as ultra high speed signal transmission:

WHY TERMINATE CABLES?

Say you send a single transition (part of a square wave clock down) down a properly terminated cable. Say real fast rise from 0 to 5V.  
Lets next have some mismatch between cable impedance and the termination resistor. What happens?
The signal travels down the cable (at about 8nSec per foot – 3/4 the speed of light or so).  
If the termination is higher than the cable, say by 10%, when the transition gets to the cable end, about 5% (1/4V) gets added to the signal. That 1/4V now travels towards the clock source. When it gets there, it normally sees a near AC short, so it becomes inverted (-1/4V) and it now travels back to the load. There again we get about 5% (half the mismatch) of the new arrival – about 12.5mV reflected back to the source. Again it gets inverted and resent…  This of course will continue to go back and forth between source and load. The good thing is it decays down.

What if the load resistance is lower by 10% than cable impedance? It is a similar story. The reflections at the load are still 5% but inverted.

I do not wish to confuse anyone. But just think of the fact that such a mess of back and forth takes place for each and every transition in WC or AES. So the reason to PROPERLY TERMINATE is to have NO REFLECTIONS.

REAL WORLD PRACTICE

How real is the reflection issue? We assumed so far the transitions are very fast. Of course one can forget about transitions at DC or for very slow voltage changes. So the question is: what is “slow”? Slow (or fast) rise is always in reference to cable length. Digital signal transmission engineers look at the ratio between cable length and rise time. A 1 inch cable (150 pSec delay) is not a problem for a 10nSec rise time. But 100nSec cable is!  

For clocks, one has to also account for the time between transitions. A WC signal puts out a transition, and may cause a bunch of reflection activity due to mismatch. We have say 11uSec between transitions (for 44.1KHz square wave WC) thus “a lot of time” for decaying to take place. Each reflection is lower than the previous, and we have a lot of time for many back and forth action, thus decay. But say we use AES with transition rates in the MHz – much less than a 1uSec time for back and forth action before the next transition… The reflection decay is not as complete.

A new transition occurring before an incomplete decay is undesirable! We end up with interaction between cable length (delay) and AES data. Making it the “same data” (digital black) does NOT make for a repetitive behavior! With “everything rattling all over the place at the same time” the voltage levels on each point of the cable change over time, and with it comes jitter.

So, WC users can get great results with pretty bad terminations. In fact, having no termination with a reasonable short cable (say 100 feet) often works just fine. However “incorrect” the signal, it tends to be repetitive from clock edge to clock edge, and repetition is what we want most.

“AES black” users need to be much more careful with cable terminations.    

BR
Dan Lavry
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Big Bri

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Re: Proper word clock implementation
« Reply #11 on: October 04, 2004, 03:17:50 am »

Dan & BK

Thank you both for your answers. The problem comes in when using different brands of converters on one system and trying to interface with digi design 888's and usd.  I found leaving my Apogee on internal and clocking the usd via the word clock inputs, the system sounded better than by clocking with the usd and using the apogee in AMbus sync.  So, is it more correct to use the Apogee AD 8000 clock or am i causing a problem i haven't discovered yet.

Thanks Again for your answers!!
Brian  
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bobkatz

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Re: Proper word clock implementation
« Reply #12 on: October 04, 2004, 10:16:27 am »

The AD 8000 is about the only Apogee converter I'm "comfortable" with in terms of its sound quality (personal opinion). I tested it on internal and external clock with a good clock, for jitter artifacts, and it appears to perform about the same either way, which is a good sign.

If you have an FFT analyser, testing for jitter artifacts is very easy to do. See

http://www.tcelectronic.com/Default.asp?Id=1156

As to whether these artifacts correlate with audibility? This is a very difficult question. But at least you can quantify the amounts to which the converter is susceptible to external clock interference and it MAY help lead you to a conclusion as to whether you are hearing an improvement, or just a "subjective enhancement". Jitter can cause:

a) distortion (which can be perceived as euphonic)
b) image narrowing or image distortion (which can be perceived as euphonic)
c) loss of low level resolution (which can be perceived as euphonic, too!)

See what I mean!


Hope this helps,


Bob
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Re: Proper word clock implementation
« Reply #13 on: October 05, 2004, 12:46:50 pm »

bobkatz wrote on Sun, 03 October 2004 23:20



  All PLL's "reclock" so that's not the issue. It's "how well they do it", and how well the output performance actually works that counts. I have measurements of converters' jitter performance, both good and bad, in my book.




  Bob, thanks for the info, I thought older PLL?s did not recover from the shifting they perform in order to "trace" the incoming clock, good to know all do that or at least try to.

Quote:



  Doesn't ADAT really require a word clock anyway?  If that's the case, then ADAT sync would be irrelevant, except to the extent that clocks and power and grounds can interact in a poorly-designed box.




No, ADAT carries clock in its optical cable, together with 8 channels (@44.1 and 48) of audio signal.

Quote:

Quote:



     I have apogee AD. Optical cable to feed converted signals and clock to computer interfaces. Word clock cable to feed clock to Yamaha 03d console that also receive signal but no clock optically from computer interface. Would it be a better way???

     Is there potential problem with feeding parallely two sources instead of the usual serial A to B, B to C ???




Hans, can you please repeat the above, more slowly  Smile.  

1) What is the block diagram of your interconnections
2) What functions as the clock master?
3) What A/D and D/A converters do you use in this block diagram and what are their functions (monitoring, mixdown, etc.)




OK Bob, sorry for not being clear, the signal flow is:

Apogee converters?s optical out to MOTU 2408 MKIII optical in. (master clock is Apogee AD, MOTU?s clock is set to optical in). A BNC cable goes from WC of the Apogee AD to the Yamaha 03d WC in. (Yamaha clock is set to WC input). MOTU 2408 optical outs goes to Yamaha 03d optical input for control room monitoring and studios cues, but when mixing, I stay in the box.  Sounds fine to me, but anyway I was curious if you recommended otherwise.

Quote:



  That's why getting jitter right is important! However, it is important to know when jitter makes a difference and when it does not. It does not make a difference with digital to digital transfers or digital processors (EQs, compressors, etc.).

BK
Very Happy

 I knew that one, and I know the most sensitive part is the conversion.

Bob, thanks for the time you take in this and other posts, it is great to have you here.

Hans
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Re: Proper word clock implementation
« Reply #14 on: October 05, 2004, 10:51:03 pm »

punkest wrote on Tue, 05 October 2004 12:46


Hans, can you please repeat the above, more slowly  Smile.  

1) What is the block diagram of your interconnections
2) What functions as the clock master?
3) What A/D and D/A converters do you use in this block diagram and what are their functions (monitoring, mixdown, etc.)




OK Bob, sorry for not being clear, the signal flow is:

Apogee converters?s optical out to MOTU 2408 MKIII optical in. (master clock is Apogee AD, MOTU?s clock is set to optical in). A BNC cable goes from WC of the Apogee AD to the Yamaha 03d WC in. (Yamaha clock is set to WC input). MOTU 2408 optical outs goes to Yamaha 03d optical input for control room monitoring and studios cues, but when mixing, I stay in the box.  Sounds fine to me, but anyway I was curious if you recommended otherwise.

[/quote]

Hans, thanks for your nice thoughts. I enjoy being here, and even when I'm answering a question, I learn something.

Let's see. As far as I can see, I think it's a good idea you're using the Apogee's as the master clock. They're certainly going to do better on internal sync than locking to any of the other current devices in your system. And only a measurement and listening test of the Apogee's would reveal if they would do better when fed some external "high-end" clock. And if they did do better on external sync, that would be a denigration of the Apogees, not a praise of the external clock. As long as you are not using the converters of the Yamaha and mixing in the box, you are doing fine from the point of view of clocking but you certainly should expand your horizons and look into a good set of high quality outboard processing gear. Your weakest link in this setup is actually your monitoring, and you can solve that by using a high quality jitter-immune external  D/A converter and monitor level control for monitoring. The 2408 goes digitally into the Yamaha, and is processed digitally, so jitter is irrelevant there, and thus only the monitor DAC is in trouble, and the Yamaha's DAC is probably suffering there from point of view of jitter.

Where you are going to run into trouble is when you introduce external analog processing gear. And for that, I would recommend that on each analog insert you use the digital outs of the Yamaha to feed higher quality external converters. A good approach would be to replace the 2-channel Apogee with a single stable 8 channel A/D/A system running on internal sync and proven to perform best that way. Use pairs of that A/D/A system for your analog processing insert, and one pair for your monitoring DAC. You can do that with digital audio routing and still maintain that A/D/A as internal clock to drive the Yamaha and other gear.

That's my take on the affair!
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