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Author Topic: SAR ADC schematic  (Read 9754 times)

Alex_M

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SAR ADC schematic
« on: October 01, 2006, 01:51:24 am »

I look for schema of Apogee AD-500 A/D converter.
What chipset is used?
Also interesting input LPF and buffer with good CMRR at high freq.

AD-500 common mode rejection is:
better than 90dB at 100Hz
better than 70dB at 10kHz

New delta-sigma hardware become worse in this parameter.
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danlavry

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Re: SAR ADC schematic
« Reply #1 on: October 03, 2006, 03:24:11 pm »

Alex_M wrote on Sun, 01 October 2006 06:51

I look for schema of Apogee AD-500 A/D converter.
What chipset is used?
Also interesting input LPF and buffer with good CMRR at high freq.

AD-500 common mode rejection is:
better than 90dB at 100Hz
better than 70dB at 10kHz

New delta-sigma hardware become worse in this parameter.


One needs to know what to design for. In my view, one needs a lot more rejection at line frequency then it does at say 10KHz. Why? Because one can have an audio cable leading to an AD input run in parallel (and not too far) to an AC line, carrying a lot of power (relatively speaking) thus pick up a lot of common mode signal. As a rule, I can not think of "everyday case" where your AD input cable will be running in parallel to a cable with 110V (or 220V) with say some .1A (or 5A) at 10KHz.

I am not against good common mode at higher frequencies, but I pay most attention to common mode at 50-60Hz and at 100-120Hz.

Each LavryBlue AD channel is adjusted by hand to better then 100dB for up to 1KHz which includes line frequencies, and is certainly better then 70dB at 10KHz... We adjust it at the max voltage level that the Audio Precision is capable of providing for common mode!

As a rule, I would not blame the sigma delta technology for common mode, because most of the issue belongs to the analog front end, way before the signal gets to the AD.

Say you have some balanced line with some common mode signal, and your front end does not reject it. Then your AD will treat the un rejected signal as if it were intended to be there.

Of course, the specification for common mode rejection on an AD chip may be important as well to insure proper design. Most modern sigma delta receive balanced input and relay on good balance. But this is a different issue. If we are to be talking about common mode, then the pre sigma delta AD's had 0dB rejection, they were single ended, and the rejection of the PRODUCT was all in the AD analog front end...

Regards
Dan Lavry
http://www.lavryengineering.com        
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Alex_M

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Re: SAR ADC schematic
« Reply #2 on: October 08, 2006, 08:02:47 pm »

danlavry wrote on Tue, 03 October 2006 14:24

In my view, one needs a lot more rejection at line frequency then it does at say 10KHz. Why? Because one can have an audio cable leading to an AD input run in parallel (and not too far) to an AC line, carrying a lot of power (relatively speaking) thus pick up a lot of common mode signal. As a rule, I can not think of "everyday case" where your AD input cable will be running in parallel to a cable with 110V (or 220V) with say some .1A (or 5A) at 10KHz.
Thanks.
I'm think about 30...300 kHz band (switching power sources).
Single ended A/D chip in Apogee is PCM1750?
Can You tell, how to improve CMRR performance of differential-input ADC chips (i.e. AK5394, AD7690) up to 90 dB in audio band? Convert balanced input to unbalanced and back to differential?
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danlavry

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Re: SAR ADC schematic
« Reply #3 on: October 09, 2006, 01:39:43 pm »

Alex_M wrote on Mon, 09 October 2006 01:02

danlavry wrote on Tue, 03 October 2006 14:24

In my view, one needs a lot more rejection at line frequency then it does at say 10KHz. Why? Because one can have an audio cable leading to an AD input run in parallel (and not too far) to an AC line, carrying a lot of power (relatively speaking) thus pick up a lot of common mode signal. As a rule, I can not think of "everyday case" where your AD input cable will be running in parallel to a cable with 110V (or 220V) with say some .1A (or 5A) at 10KHz.
Thanks.
I'm think about 30...300 kHz band (switching power sources).
Single ended A/D chip in Apogee is PCM1750?
Can You tell, how to improve CMRR performance of differential-input ADC chips (i.e. AK5394, AD7690) up to 90 dB in audio band? Convert balanced input to unbalanced and back to differential?



I really can not provide designs on the forum. getting 90dB over audio will take more then what you suggested.

Regards
Dan Lavry
http://www.lavryengineering.com
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abirkett

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Re: SAR ADC schematic
« Reply #4 on: November 20, 2006, 09:24:01 am »

I would firtsly try and track down the offending switching supplies and tame their EMC.

Common mode chokes at the input often help, especially if followed by small caps to ground from the signal pair.

If this is fails, then you can make a line receiver from an AD8130/AD8129 which has a CMRR of well over 100db@100kHz. I have used these devices to great effect in video systems.
See AD8129/30 datasheet:

http://www.analog.com/UploadedFiles/Data_Sheets/AD8129_8130. pdf


Choose Zi and Zo to suit your needs. DC offset is less than 5mV
and can be trimmed by lifting U2s + terminal and injecting an offset voltage.
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danlavry

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Re: SAR ADC schematic
« Reply #5 on: November 20, 2006, 02:39:10 pm »

abirkett wrote on Mon, 20 November 2006 14:24

I would firtsly try and track down the offending switching supplies and tame their EMC.

Common mode chokes at the input often help, especially if followed by small caps to ground from the signal pair.

If this is fails, then you can make a line receiver from an AD8130/AD8129 which has a CMRR of well over 100db@100kHz. I have used these devices to great effect in video systems.
See AD8129/30 datasheet:

 http://www.analog.com/UploadedFiles/Data_Sheets/AD8129_8130. pdf


Choose Zi and Zo to suit your needs. DC offset is less than 5mV
and can be trimmed by lifting U2s + terminal and injecting an offset voltage.



The 8130 is not aimed at audio. The distortion figure is too high and it just does not fit audio.

Also, one needs to see the distinction between power supply rejection and common mode rejection.

PSRR (power supply rejection ratio) is telling us the amount of noise that will get to the device output when the power supply line has noise on it.

CMRR (common mode rejection ratio) applies to balanced drive, it tells us how much signal will get to the device output when both inputs (balanced drive) move up and down together. For testing it, we often just tie the 2 inputs together, and apply a common signal to both.

Of course, noise from a power supply may find its way to the output via either mechanism: Directly from the power supply lines (PSRR) or via coupling to the inputs.

Regrads
Dan Lavry
http://www.lavryengineering.com
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